1. Field of the Invention
The present invention relates to use of shared memory between multiple processors for communicating command messages and payload data therebetween. More particularly, it relates to an efficient architecture and system design for efficiently assigning shared memory locations as a full duplex mailbox.
2. Background of Related Art
Digital memory is found in nearly every digital electronic device, particularly when such device includes a processor (e.g., a microprocessor, microcontroller, or digital signal processor). Many types of digital memory exist, perhaps the most common form being random access memory (RAM).
With advancements in technology came the need to include more than one processor in a device. While each processor (or other) device has its own assigned tasks, information is typically made available to either processor through the use of a commonly accessible memory, e.g., RAM. This commonly accessible memory may be dual port memory or simply a shared memory area having an individual address and data bus (i.e., port) for each accessing processor.
Two processors (e.g., a microprocessor unit (MPU) and a digital signal processor (DSP)) may utilize shared memory to cooperatively pass command information to one another, and/or to pass more lengthy payload data (e.g., digitized voice messages) back and forth. Such a use of the shared memory is often referred to as a “shared mailbox” or simply a “mailbox”.
In a shared memory mailbox, a first processor or other device writes to a particular address/data location(s) of the shared memory, and the second processor or other device reads from that particular address/data location(s).
FIG. 4 shows a conventional shared memory 504, e.g., a dual port memory, serving as a message mailbox between two processors. In FIG. 4, the shared memory 504 has a first port 579 including an address and data bus connected to a first processor 500, and a second port 589 including another address and data bus connected to a second processor 502.
Depending upon the particular application, an incoming mailbox and an outgoing mailbox for a particular processor may be of different sizes. For instance, in FIG. 4, the shared memory 504 is configured for use by either processor 500, 502 by providing a moveable partition in the memory space of the common memory 504. For instance, if the common memory 504 is a 2K word memory, the first 1K (i.e., 0 to 1K) may be assigned for use by the first processor 500 while the second 1K (i.e., 1K to 2K) may be assigned for use by the second processor 502. The partitioned portions of the shared memory are mapped into the memory map of the respective processors, and form the boundaries of the two mailboxes providing bi-directional messaging between the two processors 500, 502.
The challenges of using a dual access RAM or other shared memory 504 to pass messages between processors 500, 502 are well known. For instance, use of the shared, common memory 504 as a message mailbox between the two processors 500, 502, requires that both processors 500, 502 have access to common memory locations. To pass messages from the first processor 500 to the second processor 502, the first processor 500 must be given write access to that particular memory location, and the second processor 502 must be given read access to read that same memory location to receive the message.
As shown in FIG. 5, from an external perspective, it appears as if either processor 500, 502 can access any memory location 530–545 in the shared memory 504 at any time. For instance, in the example shown in FIG. 5, the first processor 500 is addressing memory location 535, and the memory location 535 is allowing an appropriate write operation (or other operation) on the first data bus DATA 1 corresponding to the first processor 500. At the same time, the second processor 502 is accessing memory location 542 using its corresponding address and data buses ADDR 2, DATA 2.
The example of FIG. 5 shows proper simultaneous access to separate and distinct memory locations 535 and 542 by the respective processors 500, 502 using conventional dual port memory 504. However, as shown in the example of FIG. 6, a collision would occur in the event that both processors 500, 502 try to simultaneously write to the same memory location 542. In this case, an unpredictable state would occur with respect to data output on the respective data buses DATA 1, DATA 2.
Conflicts may occur between the two processors 500, 502, e.g., if an access from either processor 500, 502 to any particular memory location is overlapped with an access by the other. Thus, designers attempt to avoid race conditions and corruption of data caused by the potential for simultaneous or substantially simultaneous access of a particular memory location by both processors 500, 502.
To avoid overwriting or otherwise colliding with each other's data space, the shared memory 504 can be physically or logically separated into two mailbox segments. This technique works, but is not flexible enough to efficiently accommodate large payload data transfers from either processor to the other without requiring reconfiguring of the partition in the shared memory 504 between the mailbox message directions.
Another conventional method provides for dynamic allocation of the shared memory space 504 to only one processor at a time to avoid collisions (i.e., multiplexed access), but this technique does not maximize use of the shared data space, slows down full duplex (i.e., bi-directional) message transfer, and causes some longer payload messages to be passed in non-contiguous portions of the shared memory 504 which also slows down data transfer of the payload data from the shared memory 504 by the receiving processor.
Another technique to prevent collisions in accesses to common memory is to synchronize the accesses of the two processors 500, 502 to be not coincidental in time with one another, e.g., allowing alternating access on a word or other basis by the two processors 500, 502 to the shared memory 504. However, this technique slows down the data or payload transfer rate in both directions.
There is a need for an efficient technique and apparatus for using shared memory to form a bi-directional mailbox for command messages and/or payload data between two processors.